Abstract
A novel Quatro-based flip-flop design with low penalty was proposed. By utilizing layout technique, SEU hardness was achieved in this design because of charge sharing between the introduced PMOS transistors. Both the proposed design and the reference flip-flop were fabricated in a 65 nm standard CMOS technology. The pulsed laser experiment results demonstrate that the new design has a larger upset threshold and lower SEU error rate compared with the reference. The area and delay penalties are not significant, i.e., 13% and 37%, respectively.
Published Version
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