Abstract
Problem statement: Compression is useful because it helps reduce the consumption of expensive resources, such as hard disk space or transmission bandwidth. For effective data compression, the compression algorithm must be able to predict future data accurately in order to build a good probabilistic model for compression. Lossless compression is essential in cases where it is important that the original and the decompressed data be identical, or where deviations from the original data could be deleterious. Approach: Prediction by Partial Matching (PPM) data compression technique had utmost performance standard and capable of very good compression on a variety of data. In this research, we had introduced PPM technique to compress the data and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The PPM algorithm was modeled using the hardware description language VHDL. Results: Functional simulations were commenced to verify the functionality of the system with both 16-bit input and 32-bit input. The FPGA utilized 1164 logic cells with a maximum system frequency of 95.3MHz on Altera FLEX10K. Conclusion: The proposed approach is computationally simple, accurate and exhibits a good balance of flexibility, speed, size and design cycle time.
Highlights
Data compression is an essential process due to the need to reduce the average time required to send messages and reduce the data size for storage purposes
There is a vital need for lossless compression especially for text and binary compression as it is important to ensure that the restructured text is identical to the original text, because a very small difference or variation in statement can lead to total different meaning
Prediction by Partial Matching (PPM) is a “finite context” statistical modeling technique that can be viewed as blending several “fixed-order context” models to predict the character in the input sequence
Summary
Data compression is an essential process due to the need to reduce the average time required to send messages and reduce the data size for storage purposes. The original algorithm was first published in 1984 by Cleary and Witten (1984) and a series of improvements was described by Moffat (1990) culminating in a careful implementation, called PPMC, which has become the benchmark version This still achieves results superior to virtually all other compression methods, despite many attempts to better it. Each block consists of programmable look-up table and storage registers, where interconnections among these blocks are programmed through the hardware description language (Reaz et al, 2003; 2004; 2005) This programmability and simplicity of FPGA made it favorable for prototyping digital system. A unified framework for FPGA realization of PPM is designed by means of using a standard hardware description language VHDL for two different input sizes 16-bit and 32-bit. The method provides a systematic approach for hardware realization, facilitating the rapid prototyping of the data compression system
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