A Simulation-Based Study on Memory Design Issues for Embedded Systems

Abstract

Due to the increasing gap between the speed of CPU and memory, cache designs have become an increasingly critical performance factor in microprocessor systems. Recent improvements in microprocessor technology have provided significant gains in processor speed. This dramatic rise has increased further the gap between the speed of the processor and main memory. Thus, it is necessary to design faster memory systems. In order to decrease the processor–memory speed gap, one of the main concerns has to be in the design of an effective memory hierarchy including multilevel cache and TLB (Translation Lookaside Buffer). On the other hand, a notable part of the computer industry nowadays is involved in embedded systems. Embedded systems play a significant role in almost all domains of human activities including military campaigns, aeronautics, mobile communications, sensor networks, and industrial local communications. Timeliness of reactions is necessary in these systems and offline guarantees have to be derived using safe methods. Hardware architectures used in such systems now feature caches, deep pipelines, and all kinds of speculations to improve average-case performance. The speed and size are two important concerns of embedded systems in the area of memory architecture design. In these systems, it is necessary to reduce the size of memory to obtain better performance. Real-time embedded systems often have a hard deadline to complete some instructions. In these cases, the speed of memory plays an important role in system performance. Cache hits usually take one or two processor cycles, whereas cache misses take tens of cycles as a penalty of mishandling and so the speed of memory hierarchy is a key factor in the system. Almost all embedded processors have on-chip instructions and data caches. From a size point of view, it is critical for battery-operated embedded systems to reduce the amount of consumed power.