A simulation study on the impact of lithographic process variations on CMOS device performance

Abstract

ABSTRACT In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductordevice simulation tool can be used to investigate the impact of lithographic process variations on nano-scaledCMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancementfactor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holisticfashionasameanstoanend.Asaconsequence,theultimate“gureofmeritisdeterminedbytheperformanceof the device.Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask near“eld.TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator(UTB FD-SOI) nMOSFET, with a physical gate length of 32nm. Electrical parameters such as on- and o-current, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed andextracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyedand illustrated. Moreover, we present an adjusted lithography process window de“ned by the electrical behaviorof the device.In addition to a discussion of the obtained results, this paper also focuses on the software design aspects ofinterfacing a lithography simulation environment with a device simulator. The steps involved in extracting pa-rameters and transferring them from one program to the other are explained, and further automation capabilitiesare suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/deviceprocess optimization procedure.Keywords: Lithography Simulation, Process Simulation, Device Simulation, Process Variations