Abstract
Effects of dopant distribution in substrate/back-gate on performance and Vt roll-off of ET-SOI MOSFETs with UT-BOX (ES-UB-MOSFETs) are simulated and studied. Lateral non-uniform dopant distributions (LNDD) in substrate, for the first time, are used to enhance scaling capability and improve Vt controllability for ES-UB-MOSFETs. Process and device simulations are conducted to demonstrate the importance of substrate dopant engineering and to search the optimization design conditions for ES-UB-MOSFETs. Fixing long channel Vt at 0.3V for both bulk MOSFETs and ES-UB-MOSFETs, ES-UB-MOSFETs with LNDD can improve Ieff@Ioff= 1e-7A/μm by 20% for nMOS and 18% for pMOS. With fixing long channel Vt at 0.3V for ES-UB-MOSFETs, LNDD enables gate length to be scaled to 20nm for both nMOS and pMOS, which is ~ 43% smaller than that of the ES-UB-MOSFETs with lateral uniform doping in substrate. A novel process flow to form LNDD is proposed and simulated.
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