A Simulation Environment for Network Processor Based on Simultaneous Multi Thread Architecture

Abstract

This study is centered on the architectural efficacy of network processors based on simultaneous multi thread (SMT) architecture that support multiple active concurrent hardware threads at the same time with the goal of sharing resources such as functional units and memory. This thread-level-parallelism can be exploited in packet processing devices called network processors. The programs running on network processors have different characteristics depending on where the is used and the input workload. In this paper , we introduce our simulation environment, called SNP (Simulator for Network Processor), for simulating a typical SMT network which includes a connected network controller and a packet generator. The presented in this study is a process based simulator for Network processor (SNP) usable for different modes and applications based on - by - clock method and is described according to SMT Structure. The architecture is performed by C++ language optimized as efficient as possible. Such is similar with simple scalar simulator.