Abstract

Abstract This paper introduces a computational approach to three dimensional component layout that employs simulated annealing to generate optimal solutions. Simulated annealing has been used extensively for two dimensional layout of VLSI circuits; this research extends techniques developed for two dimensional layout optimization to three dimensional problems which are more representative of mechanical engineering applications. In many of these applications, miniaturization trends increase the need to achieve higher packing density and fit components into smaller containers. This research addresses the three dimensional packing problem, which is a subset of the general component layout problem, as a framework in which to solve general layout problems.

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