A Simplified Method for Patterning Graphene on Dielectric Layers.

Håkon I Røst,Anton Tadich,Frode S Strand,Simon P Cooil,Daniel M Gottlob,Thomas Schmidt,Rajesh Kumar Chellappan,D Andrew Evans,Bruce C C Cowie,Benjamen P Reed,Justin W Wells,Gary Wan,Lucas De Souza Caldas,Mauricio J Prieto,Antonija Grubišić-Čabo,Joseph A Durk,Liviu C Tănase,Mattia Cattelan

doi:10.1021/acsami.1c09987

Abstract

The large-scale formation of patterned, quasi-freestanding graphene structures supported on a dielectric has so far been limited by the need to transfer the graphene onto a suitable substrate and contamination from the associated processing steps. We report μm scale, few-layer graphene structures formed at moderate temperatures (600–700 °C) and supported directly on an interfacial dielectric formed by oxidizing Si layers at the graphene/substrate interface. We show that the thickness of this underlying dielectric support can be tailored further by an additional Si intercalation of the graphene prior to oxidation. This produces quasi-freestanding, patterned graphene on dielectric SiO2 with a tunable thickness on demand, thus facilitating a new pathway to integrated graphene microelectronics.

Highlights

The extraordinary properties and success of graphene in prototype electronic platforms have led to numerous synthesis routes and processing methods for patterning the material
Fe patterned on 6H-SiC(0001). (b) Spatially resolved Raman showing the intensity of the 2D graphene peak near the edge of one of the patterned regions. (c) Intensity and full width at half-maximum (FWHM) of the 2D Raman peak recorded from the two different spatial Regions I and II in panel 1b. (d) Small-area low-energy electron diffraction (μ-LEED) pattern of Fe-mediated, patterned graphene on 6H-SiC(0001) grown at 600 °C
Grown graphene exclusively on top of Fe islands is demonstrated in Figure 1, using Raman spectroscopy, energyfiltered photoemission electron microscopy (EF-PEEM), and low-energy electron diffraction (LEED)

Summary

Introduction

The extraordinary properties and success of graphene in prototype electronic platforms have led to numerous synthesis routes and processing methods for patterning the material. A promising transfer-free method utilizes a transition-metal catalyst (Cu or Ni) deposited directly onto an oxide layer on a Si wafer.[22,23] Graphene is formed by annealing in the presence of carbon, and the metal film is subsequently removed chemically, leaving the graphene in direct contact with the dielectric material This method shows great potential, metal contamination remains a major issue.[24] An alternative approach for removing metal from the graphene has been demonstrated,[25] as has a method for adding a dielectric layer under the graphene after growth.[26] Both modify the graphene−substrate interaction, which is known to impact the electronic properties of graphene.[27−30] there is no single method that suits all device applications, there is a desire for transfer-free methods that produce graphene free of contaminants and with control of the substrate interaction, directly on dielectric surfaces. We demonstrate transfer-free, patterned graphene structures on SiC, with optional decoupling by forming SiO2 at the graphene− semiconductor interface

Methods

Results

Conclusion