A Simplified Design Model for Random Process Variability

Abstract

A method for modeling the effects of random process variation through measured transistor current is introduced. The methodology culminates by modeling random current variation at a given operating point above threshold as a zero-mean Additive White Gaussian Noise (AWGN) current source with a standard deviation dependent on nominal operating current and design variables, the transistor sizes, W and L, and the transistor operating points, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> . The model has a simple posynomial form and is accurate compared to measured data within an RMS error of 5.4% for narrow-, wide-, short-, and long-channel transistors. The model's simplified form bridges the gap between existing statistical methods and circuit design. The efficacy of the model in the circuit design space will also be presented. In the analog domain, we will show that the contributions of this model can be used as a replacement for Monte Carlo methods for calculating circuit voltage and current variances. In the digital space, we will investigate the calculation of timing delay distributions. Results calculated via an alpha-power (α <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) law model for average current show that scaling the supply voltage by γ results in an approximately 1/γ scaling in the path-delay standard deviation for a 65-nm process.