A simplified and efficient implementation of FPGA-based turbo decoder

Abstract

In the max-log-MAP decoding algorithm, the branch metrics are modified by weighting a-priori values by a suitable scaling factor, resulting in a significant BER improvement. Using integer arithmetic and proper hardware management, an efficient implementation of a turbo decoder based on the modified form of max-log-MAP algorithm is proposed. All internal metrics are represented and operated on integers, avoiding complex calculation seen in floating and fixed-point arithmetic. The turbo decoder is implemented by a careful manipulation of the hardware with a single decoder structure without any interleaving and de-interleaving delay, resulting high data throughput with very low FPGA resource utilization. The final FPGA design consumes approximately 695 mW to achieve throughput of more than 1 Mbps with eight iterations. With channel inputs of only 3 bits (8 levels), the integer version of turbo decoder results in less than 0.5 dB loss of E/sub b//N/sub o/ from the optimal floating point turbo decoder.