A simple technique for failure analysis of MOS IC using liquid crystal : Takahisa Yamaha and Sotaro Nakano. Proc. 15th Symp. Reliab. Maintainab. (Union of Japanese Scientists and Engineers, Tokyo), 57 (1985)

Abstract

In this paper, high-linearity CMOS single-pole-double-throw (SPDT) RF switches using the proposed field-plate (FP) transistors were fabricated and compared. The 0.13-μm CMOS processed FP metal was connected to the gate terminal and source terminal individually. The discussion throughout dc characteristic, linearity, and power property was given. The gate-terminated FP (FP-G) NMOS provided a lower gate resistance being confirmed for low-noise and high-efficiency design while the source-terminated FP (FP-S) NMOS with relatively lower leakage current, higher linearity, and higher breakdown under high Vds is confirmed to be suitable for high-linearity power design. Several switches using standard transistor, FP-S, and FP-G NMOS transistors were implemented and analyzed. Comparison on the switch characteristics and application has been done. The novel designs indicated that the proposed FP-based switches provided good potentials in power handling and harmonics rejection without sacrifice of power consumption, chip area, and insertion loss.