A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs

Abstract

For FPGA applications in the application domains requiring a high degree of functional safety such as automotive and industrial infrastructure, simple homogeneous redundant logic design, where the same hardware modules are simply replicated, is not enough. In order to improve tolerance to common cause fault, heterogeneous redundant design, where different implementation approaches are taken for realizing the same logic functionality, is crucial. However, manual redundant design tends to place a burden on designers, reducing productivity of system development. To cope with this problem, this paper proposes a systematic heterogeneous redundant design approach for finite state machines on FPGAs, focusing on the diversity of state encoding methods. With this approach, designers can easily combine the state machines with different encoding to form heterogeneous redundancy, by inserting simple directives into RTL source code. In order to evaluate the effectiveness of the proposed approach, timing analysis of post-layout netlists is performed under an overclock situation as an example of common cause fault. The evaluation results demonstrate the proposed approach improves the error detection rate compared to conventional homogeneous redundant designs. It is also discussed how the choice of state encoding methods impacts the error detection rate.