A simple & cost-effective novel methodology for predicting SSN system performance for different PCB trace lengths

Abstract

High data rates, high clock speeds, and low power consumption are synonymous with advanced electronic devices. Consequently, simultaneous switching noise (SSN) is emerging as a critical side-effect of toggling signals within an electronic device because SSN affects signal integrity. Even minute changes in signal voltage in the order of a few millivolts can adversely affect the functioning of a circuit. A PCB typically forms the communication backbone between electronic components including field programmable gate array (FPGA) devices. Signal quality and SSN effects vary with PCB trace lengths. Traditionally, complex board models are used to simulate the SSN characteristics of electronic devices for different PCBs, which can be time consuming and expensive. This paper presents a cost-effective novel methodology for de-embedding the PCB trace effect to accurately characterize an FPGA device's intrinsic SSN characteristics. The methodology uses simple and fast measurement and simulation techniques to de-embed the PCB trace effect for different PCB trace lengths. The predicted SSN data for different PCB trace lengths and intrinsic SSN data obtained using this methodology will be useful to FPGA system designers.