Abstract
This paper reports the fabrication of vertical junction field-effect transistors (v-JFETs) with standard 0.7 μm CMOS technology. The process flow is described and the device feasibility is demonstrated. The measured electrical and frequency performances are in good agreement with the simulation results when parasitic capacitances, inherent to the non-optimised layout presently used, are taken into account. It is shown that, with a specific interdigited mask design, a transit frequency higher than 10 GHz could be achieved with a 1.6 μm periodicity.
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