Abstract
A sideband-suppressed China UWB Standard synthesizer which is able to generate two carriers simultaneously is presented. An efficient synthesizing technique with a single quadrature phase-locked loop (QPLL) is proposed for fast band switching. To suppress accumulating sidebands at the outputs, a clock buffer with I/Q calibration and distortion cancellation technique is proposed. Fabricated in TSMC 0.13-μm CMOS technology and operated at 1.2 V, the synthesizer measures a maximum sideband rejection of 45 dB and a phase noise of ?105 dBc/Hz at 1-MHz offset. The synthesizer covers frequency range from 6.2 to 9.4 GHz with band switching time less than 1.4 ns.
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