A SEU Immune Flip-Flop with Low Overhead

Abstract

AbstractIn nano-scale CMOS technologies, storage cells such as flip-flops are becoming increasingly sensitive to soft errors caused by harsh radiation effects. This paper proposes a radiation-hardened flip-flop with single event upset (SEU) immunity and low overhead. The flip-flop consists of a transfer unit, a storage unit and an output stage. The input signal propagates through transfer unit to the storage unit on the rising edge of the clock signal. The transfer unit uses the true single-phase clock (TSPC) scheme to simplify the clock distribution and reduce power consumption. The storage unit is composed of a radiation hardened memory (RHM) cell. Due to stacked PMOS structure and interlocked interconnect mechanism, SEU can be entirely tolerated. The C-element at output stage can filter any SEU occurred at storage unit. Compared with the existing radiation hardened flip-flops, the proposed flip-flop achieves 41.4% reduction in terms of delay on average, 82.6% reduction in terms of active power on average, 83.8% reduction in terms of power delay product on average and 39.7% reduction in terms of area on average.KeywordsSingle event upsetTrue single-phase clockC-element