A Semiparallel Full-Adder in IMPLY Logic

Abstract

Passive implementation of memristors has led to several innovative works in the field of electronics. Despite being primarily a candidate for memory applications, memristors have proven to be beneficial in several other circuits and applications as well. One of the use cases is the implementation of digital circuits such as adders. Among several logic implementations using memristors, IMPLY logic is one of the promising candidates and one of the first stateful logics proposed. In this logic, the result of a IMPLY b (a → b) is stored in b and it is always true (1) except for when a=0 and b=1. Given the intrinsic difference between IMPLY and Boolean logic, conventional operations such as binary addition need to be appropriated for implementation using IMPLY. This appropriation has two main constituents; the topology or structure of the adder and the algorithm performing the addition. In this paper, we proposed a new architecture for a digital full-adder, which is up to 41% faster than existing IMPLY-based serial designs while requiring up to 78% less area (memristors) compared to the existing parallel design. In addition to that, we present a review of the state-of-the-art in IMPLY-based adders, which appeared in the literature during the last five years and discuss their advantages or disadvantages. To be able to compare these designs in a generic condition, we define a Figure of Merit (FoM), in which both the number of memristors (n m ) and the number of steps (n s ) are equally important. However, we must bear in mind that m (which translates to area and consequently cost) and s (which represents the speed of the full-adder) carry different weights in designs with different constraints. IMPLY-based adders can be divided into two major micro-architectures; i) serial, in which each bit is processed after the other, ii) parallel, in which bits are added in parallel as long as possible. In the first category, relatively speaking, the number of memristors is low and the number of steps is high. This is quite the opposite for the second category. In serial adders, [1] is one of the very first efficient designs, which needs 3n+3 memristors and 29n steps for an n-bit addition. In [2], a different algorithm led to a smaller number of steps, i.e., 23n. These works were improved in terms of FoM, thanks to a new approach proposed in [3], where input memristors were used for storing the output result too. Thus, the new algorithm managed to reduce m and consequently increase FoM, without needing any structural changes. However, this approach, which was adopted by [4] as well, is not suitable for all applications, in particular when the respective input is needed for further operations and its value must not be lost. The parallel design proposed in [1] was for a long time uncontested until recently the authors in [4] proposed an approach, which reduced n m and thus improved FoM by applying a minimal change to the structure. Lastly, in our newer topology, namely semiparallel topology, by having two serial sections in parallel, we managed to considerably reduce the number of steps (compared to serial adders), without needing any additional memristors. The FoM of this design is even better than the parallel approach proposed in [4]. Compared to other serial works our design needs three extra switches, which is negligible compared to 2n and n switches required in the parallel approaches.