A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement

Abstract

STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) is a potential candidate for the requirement of many IoT and wearable device, which thanks to its fast write speed, negligible leakage current, and high endurance. Nevertheless, the challenge of STT-MRAM voltagemode read scheme still exist, firstly, the bit line (BL) voltage (V BL ) drops from the pre-charge read voltage (V BL_RD ) to 0V quite quickly, which can result in a small effective sensing window (T SMW ), which is the period when the sense amplifier’s (SA) input voltage larger than its offset voltage (V OS ). The second issue is that the occurrence time of maximum read- signal margin (V RSM ) usually is different in different cells due to the resistance variation. Consequently, the valid T SMW is quite small, and the limited T SMW leads to a decrease of V RSM and an increase of BL development time. When a conventional voltage-mode sense amplifier (VSA) is used with a common activated timing, the signal to be amplified will encounter degradation at the VSA’s differential inputs and lead to a sensing failure at a low V BL_RD . This paper proposes a selftimed sensing unit that can dynamically track the change of BL voltage, a couple SAs in the unit are reconfigured to the opposite offset states to monitor each other’s sensing results, and the sensing operation is immediately stopped when the sensing result is correct. The simulation results show that the proposed architecture can extend T SMW significantly and the sensing yield will be improved effectively.