A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management

Abstract

Accurate estimation of the silicon junction (or die) temperature in high-end microprocessors is crucial for various performance analyses and also for chip-level thermal management. This work introduces for the first time, the notion of self-consistency in estimating the die temperature for sub-100 nm CMOS technologies by taking into account various electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature. It also comprehends chip-level reliability constraints and the impact of employing various packaging and cooling solutions in an integrated manner. The self-consistent solutions of die temperature are shown to have significant implications for evaluating various power-performance-reliability-cooling cost tradeoffs and can be used to optimize the performance of nanoscale ICs.