A self-calibrated multiphase timing system in time-interleaved ADC

Abstract

A precise timing system that consists of two delay-locked loops (DLLs) is proposed to align the sampling phases of the time-interleaved ADC (TI-ADC) with the front-end Sample and Hold (S/H) clock. DLL1 using bang-bang phase detector (PD) handles the 1 GHz system clock and DLL2 produces 32 phases to generate the non-overlapped clock in the followed 4 pipeline ADCs. A new self-calibration scheme in DLL2 is proposed to reduce the mismatch-induced timing skew among multiphase clocks, thereby improving the performance of the S/H in the gain phase. The timing system is verified in 0.18 um CMOS process. The simulation results show that the precision of the calibration loop is 5 ps covering ±75 ps range.