A self-rectifying TaOy/nanoporous TaOx memristor synaptic array for learning and energy-efficient neuromorphic systems

Sanghyeon Choi,Kyung-Jin Lee,Seonghoon Jang,Hu Young Jeong,Gunuk Wang,Jong Chan Kim,Peonghwa Jang,Jung-Hwan Moon

doi:10.1038/s41427-018-0101-y

Abstract

The human brain intrinsically operates with a large number of synapses, more than 1015. Therefore, one of the most critical requirements for constructing artificial neural networks (ANNs) is to achieve extremely dense synaptic array devices, for which the crossbar architecture containing an artificial synaptic node at each cross is indispensable. However, crossbar arrays suffer from the undesired leakage of signals through neighboring cells, which is a major challenge for implementing ANNs. In this work, we show that this challenge can be overcome by using Pt/TaOy/nanoporous (NP) TaOx/Ta memristor synapses because of their self-rectifying behavior, which is capable of suppressing unwanted leakage pathways. Moreover, our synaptic device exhibits high non-linearity (up to 104), low synapse coupling (S.C, up to 4.00 × 10−5), acceptable endurance (5000 cycles at 85 °C), sweeping (1000 sweeps), retention stability and acceptable cell uniformity. We also demonstrated essential synaptic functions, such as long-term potentiation (LTP), long-term depression (LTD), and spiking-timing-dependent plasticity (STDP), and simulated the recognition accuracy depending on the S.C for MNIST handwritten digit images. Based on the average S.C (1.60 × 10−4) in the fabricated crossbar array, we confirmed that our memristive synapse was able to achieve an 89.08% recognition accuracy after only 15 training epochs.

Highlights

IntroductionOver the past few decades, von Neumann architecture with Si-based complementary metal-oxide-semiconductor (CMOS) technology has served as a mainstay of the modern computer and electronics industries.[1,2] the impending fundamental physical limits of CMOS technology and increased fabrication cost have become the main obstacles to sustainable computing technology envisioned for the future.[1,3,4] In the big data era, the explosive growth of unstructured data and data complexity have revealed the limits of classical computing hardware in terms of the von Neumann bottleneck between processor and memory,[5] the rapid increase of heat flux due to CMOS scaling,[6] and device packing density restriction due to local energy dissipation.[7]The neuromorphic electronic system, which imitates the principles of biological synapses in a huge network of neurons, has emerged as a promising approach for implementing exceptionally energy-efficient, time-efficient, and fault-tolerant computing technologies.[8,9] Many attempts to implement the essential synaptic functions, such as short- and long-term plasticity and spike-timing dependent plasticity (STDP), have resulted in various device architectures, including memristors,[10,11,12,13,14] phase change memory,[15,16] and floating-gate transistors.[17,18]Among these devices, memristors, which consist of a simple storage medium sandwiched between two conductors, are strong candidates for device platforms for
We demonstrated essential synaptic functions, such as long-term potentiation (LTP), long-term depression (LTD), and spiking-timing-dependent plasticity (STDP), and simulated the recognition accuracy depending on the S.C for MNIST handwritten digit images
Considering the average experimental value of S.C (=1.60 × 10−4), we demonstrated that the trained network consisting only of our memristive synapse can achieve a recognition accuracy of 89.08% after 15 epochs for the MNIST digit images

Summary

Introduction

Over the past few decades, von Neumann architecture with Si-based complementary metal-oxide-semiconductor (CMOS) technology has served as a mainstay of the modern computer and electronics industries.[1,2] the impending fundamental physical limits of CMOS technology and increased fabrication cost have become the main obstacles to sustainable computing technology envisioned for the future.[1,3,4] In the big data era, the explosive growth of unstructured data and data complexity have revealed the limits of classical computing hardware in terms of the von Neumann bottleneck between processor and memory,[5] the rapid increase of heat flux due to CMOS scaling,[6] and device packing density restriction due to local energy dissipation.[7]The neuromorphic electronic system, which imitates the principles of biological synapses in a huge network of neurons, has emerged as a promising approach for implementing exceptionally energy-efficient, time-efficient, and fault-tolerant computing technologies.[8,9] Many attempts to implement the essential synaptic functions, such as short- and long-term plasticity and spike-timing dependent plasticity (STDP), have resulted in various device architectures, including memristors,[10,11,12,13,14] phase change memory,[15,16] and floating-gate transistors.[17,18]Among these devices, memristors, which consist of a simple storage medium sandwiched between two conductors, are strong candidates for device platforms for. The neuromorphic electronic system, which imitates the principles of biological synapses in a huge network of neurons, has emerged as a promising approach for implementing exceptionally energy-efficient, time-efficient, and fault-tolerant computing technologies.[8,9] Many attempts to implement the essential synaptic functions, such as short- and long-term plasticity and spike-timing dependent plasticity (STDP), have resulted in various device architectures, including memristors,[10,11,12,13,14] phase change memory,[15,16] and floating-gate transistors.[17,18].

Methods

Results

Conclusion