Abstract
A novel analog realization of a self-organizing neural network using switched-capacitors is presented. The design is entirely synchronous and incorporates a 'winner-take-all' circuit, as well as a circuit capable of computing the neural activity required by the dot product operation. A switched-capacitor circuit capable of implementing the basic learning law in self-organizing neural networks is also presented. The entire system, which avoids the cumbersome use of polysilicon resistors in VLSI technology, can easily form the backbone of a neurocomputer devoted to competitive learning systems. Also, the binary nature of the input pattern vectors lends itself to application areas such as pattern recognition and image processing. Design equations are presented and confirmed using HSPICE simulations. Experimental results of a breadboard version of the 'winner-take-all' circuit are also presented and verified, and a chip has been submitted for fabrication.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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