A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation

Abstract

A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented. The receiver uses pulse-radio UWB in the 3.6–5 GHz band to achieve a high energy efficiency. The proposed architecture employs a a demodulator with an automatic analog threshold-recovery and an all-digital clock-and-data-recovery synchronizer. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 79.5 dBm, 1 Mbps-normalized sensitivity for a mere 375 pJ/bit of power consumption in 65 nm LP CMOS, with aggressive duty-cycling ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\approx $</tex></formula> 30 ns ON times) combined with bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components.