A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs

Abstract

This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements.