A Secure Scan Design based on Scan Scrambling by Pseudorandom Values and Circuit Itself

Abstract

Scan-based Design-for-Testability (DfT) methodology has been employed extensively in intellectual property (IP) design to guarantee the testing efficiency. Nevertheless, it also becomes a liability for IP core security because the adversary can steal sensitive information such as secret keys by scan-based attacks. Many protection strategies have been proposed to oppose the scan-based noninvasive attacks by obfuscating the test data. Regrettably, most of these strategies incur the IP performance degradation or put forward the unacceptable resource requirement. In this paper, we propose a new secure scan design scheme, which scramble the test patterns with pseudo-random values and the test responses with selected internal nodes of the circuit. Without the knowledge of circuit design, the adversary cannot apply desired test patterns and cannot recover factual test responses. Thus, it can be prevented to deduce the sensitive information by scan attacks. Through simulation experiments and theoretical analyses, the proposed approach can guarantee the chip security with very low overhead and no impact on the testability.