A secure scan chain using a phase locking system and a reconfigurable LFSR

Abstract

Scan chains are exploited to develop attacks on cryptographic hardware to extract secret information. For a scan-enabled chip, the probability of success increases if a user has unlimited access to apply test patterns to the Circuit-Under-Test (CUT) and observe the responses. In this paper, two layers of security have been proposed to protect scan architecture against hackers. A tester authentication method utilizing a Phase Locked Loop (PLL) to encrypt the operating frequency of both CUT/Tester is presented. Moreover, the CUT authenticates the tester to grant access to the scan chain. In the test mode, the direct access to the scan flip-flops is not granted to protect their secret information against attackers. A built-in self-test scheme (BIST) using a reconfigurable LFSR is designed to test the scan flip-flops in the test mode.