Abstract
A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction
Highlights
A wide range of modern embedded processors includes both Scratchpad memory (SPM) and cache memory in their architectures to fulfill the application requirements of predictability, performance, and energy budget
This paper proposes a duplication scheme, cacheassisted duplicated SPM(CADS) to correct Single event upsets (SEUs) and Single event multiple upsets (SEMUs) in data SPM lines detected by a low-cost error detecting code
PROPOSED SCHEME: In cache-assisted duplicated SPM(CADS) to correct SEUs and SEMUs in data SPM lines detected by a lowcost error detecting code
Summary
A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction. Asapu Harika[1], Mr A. Sai Kumar Goud[2], Mr Pradeep Kumar Reddy3 1PG Scholar, 2Associate Professor, 3Associate Professor, Department of ECE, CMR Institute of Technology, Kandlakoya, Hyderabad, Telangana, India
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