A Scheme to Improve the Stability and Accuracy of Power Hardware-in-the-Loop Simulation

Abstract

Power hardware-in-the-loop (PHIL) is a state-of-the-art simulation technique that combines real-time digital simulation and hardware experiments into a closed-loop testing environment. The transportation delay or communication latency impacts the stability and accuracy of PHIL simulations. In this paper, for the purpose of synchronizing the PHIL out-put signal and promoting both the stability and accuracy of PHIL simulation, a hybrid compensation scheme is proposed to compensate for the time delay in the PHIL configuration. A model-based compensator is implemented to shift the time delay out of the PHIL closed-loop to enhance PHIL stability. A time delay compensation model and its equivalent inverse model are employed in the PHIL closed-loop to compensate for the time delay. A phase lead compensator and digital linear-phase frequency sampling filter (FSF) are candidate compensation models to compensate for the time delay and reshape the phase curve on a harmonic-by-harmonic basis. Simulations are made to validate the effectiveness of the compensation scheme.