A scheme for multiple on-chip signature checking for embedded SRAMS

Abstract

Embedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an embedded memory poses a challenge to a system test engineer, due to its limited controllability and observability. In this paper, we propose a pseudorandom built-in self test (BIST) scheme to solve this problem. Our technique is based on a test architecture known as multiple on-line signature checking (MOSC) which offers a very low aliasing probability and a high degree of confidence in testing. While the MOSC scheme is sufficiently general and applicable to any digital circuit, it can especially be optimized for circuits with embedded memories. We present interesting test scheduling algorithms that reduce the overhead of testing. On several industry-standard benchmark circuits, we report up to 35% savings in test area overhead.