A Scan Controller Concept for Low Power Scan Tests

Abstract

Test technology based on multiple parallel scan chains is widely used for production tests of integrated circuits. Beyond the problem of efficient test data compression, aspects of heat dissipation during testing have become a major matter of concern in recent years. In normal operation modes circuits may work close to their thermal limits. Therefore innovative test technologies and automatic test pattern generators (ATPG) algorithms need to generate test stimuli that utilize circuits more efficiently without causing excessive high thermal stress. For this reason a modified STUMPS architecture together with an optimization strategy is presented which aims at reduced power consumption (80 percent reduction over pure linear feedback shift register solutions) during scan test and high test compaction rates. Both aims could be weighted against each other as required.