A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Abstract

An optimized asymmetric coding strategy is proposed to improve the reliability of the NAND flash memories. The previously reported asymmetric coding reduces the data-retention error by decreasing the population of the VTH state which has higher error rate, and is measured on 4×nm NAND flash memory [1]. In [2], by increasing the number of the lowest VTH state, the proposed asymmetric coding strategy reduces the VPGM disturbance, and alleviates the floating-gate (FG)-FG coupling. And also, the program-disturb bit error rates (BERs) in 2×nm, 3×nm, and 4×nm NAND flash memories are reduced by 71%, 73%, and 89%, respectively. In this paper, the effect of asymmetric coding on the data-retention error is investigated in 2×nm NAND flash memory. From the measured results, the proposed asymmetric coding effectively increases the population of the lowest VTH state which has no data-retention error. The data-retention BERs in 2×nm, 3×nm and 4×nm NAND are decreased by 17%, 52% and 70%, respectively.