A scalable threshold logic synthesis method using ZBDDs

Abstract

A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.