A scalable DAQ system based on the DRS4 waveform digitizing chip

Abstract

Many current and future experiments require the highest temporal resolution together with large numbers of channels in the data acquisition system (DAQ) for a minimum cost. The DRS4 waveform digitizing chip allows data sampling at up to 5 Giga-samples per second (GSPS) with high amplitude resolution. The domino wave sampling method offers a significant cost and power reduction compared to a traditional flash analog-to-digital converter (ADC). This work presents a new DAQ system based on the DRS4 chip that allows continuous digitization of analog signals at 120 Mega-samples per second (MSPS) with the possibility to sample a region of interest up to a rate of 5 GSPS, thereby allowing a long event record with small dead-time in the read-out. The signal-to-noise ratio (SNR) of the system is measured to be 9.3 bit for the 120 MSPS signal and 9.6 bit for the DRS4 readout signal. Arbitrarily complex trigger logic can be built entirely in the digital domain in the read-out field-programmable gate array (FPGA). A Gigabit Ethernet link provides high-speed connectivity from the DAQ board to the backend system. Built-in board-to-board communication and the modular design of the system offer great scalability and flexibility with respect to the number of supported data channels.