A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories.

Piero Olivo,Rino Micheloni,Michele Favalli,Cristian Zambelli,Alessia Marelli

doi:10.3390/mi12070759

Abstract

Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the randomization task due to the increased dimensions of the memory array, especially along the bitlines. In this work, we propose an easy to implement, cost effective, and fully scalable with memory dimensions, randomization scheme that guarantees optimal randomization along the wordline and the bitline dimensions. At the same time, we guarantee an upper bound on the maximum length of consecutive ones and zeros along the bitline to improve the memory reliability. Our method has been validated on commercial off-the-shelf TLC 3D NAND Flash memory with respect to the Raw Bit Error Rate metric extracted in different memory working conditions.

Highlights

The 3D NAND Flash technology is the primary choice for non-volatile mass storage platforms such as Multimedia Cards (MMCs) and Solid State Drives (SSDs) [1]
We show that a chained structure of two k-bits Linear Feedback Shift Register (LFSR) can provide, from a statistical standpoint, both the horizontal and vertical data randomization while guaranteeing a k-bit upper bound on the maximum sequence length of consecutive ones and zeros; We show that our proposed randomization scheme introduces a low-complexity hardware overhead, most of which scales automatically with the memory size and is independent of cumbersome heuristics, to achieve seed randomization or lookup tables (LUTs) for seed storage, to potentially be adopted by different memory technologies and vendors; We benchmark the effectiveness of our scheme by measuring the Raw Bit Error Rate (RBER) characteristics of a Triple Level Cell (TLC) 3D NAND Flash memory during both endurance and data retention stress
In TLC architectures, all the cells belonging to a wordline can store up to three bits per cell, defined as Lower Significant Bit (LSB), Central Significant Bit (CSB) and Most Significant Bit (MSB); Bitline selectors and bitline (BL) contacts are on top of the structure

Summary

Introduction

The 3D NAND Flash technology is the primary choice for non-volatile mass storage platforms such as Multimedia Cards (MMCs) and Solid State Drives (SSDs) [1]. We show that a chained structure of two k-bits LFSRs can provide, from a statistical standpoint, both the horizontal and vertical data randomization while guaranteeing a k-bit upper bound on the maximum sequence length of consecutive ones and zeros; We show that our proposed randomization scheme introduces a low-complexity hardware overhead, most of which scales automatically with the memory size and is independent of cumbersome heuristics, to achieve seed randomization or lookup tables (LUTs) for seed storage, to potentially be adopted by different memory technologies and vendors; We benchmark the effectiveness of our scheme by measuring the RBER characteristics of a Triple Level Cell (TLC) 3D NAND Flash memory during both endurance and data retention stress

Background

Randomizers Based on LFSRs

The Proposed Solution

Experimental Validation

Conclusions