Abstract
This paper presents a cache-aware configurable hybrid flash translation layer (FTL), named CACH-FTL. It was designed based on the observation that most state-of-the-art flash-specific cache systems above FTLs flush groups of pages belonging to the same data block. CACH-FTL relies on this characteristic to optimize flash write operations placement, as large groups of pages are flushed to a block-mapped region, named BMR, whereas small groups are buffered into a page-mapped region, named PMR. Page group placement is based on a configurable threshold defining the limit under which it is more cost-effective to use page mapping (PMR) and wait for grouping more pages before flushing to the BMR. CACH-FTL is scalable in terms of mapping table size and flexible in terms of Input/Output (I/O) workload support. CACH-FTL performs very well, as the performance difference with the ideal page-mapped FTL is less than 15% in most cases and has a mean of 4% for the best CACH-FTL configurations, while using at least 78% less memory for table mapping storage on RAM.
Highlights
Semiconductor-chip-based nonvolatile memories (NVM) are becoming more widely used and are no longer confined to embedded systems
CACH-flash translation layer (FTL) splits the flash memory into two regions: (1) an over-provisioning region managed with a page-mapping scheme; and (2) a data region managed by the use of a block-mapping scheme
One can observe that for the chosen configuration, CACH-FTL approaches the performance of the ideal PM better in most cases and always performs better than block-mapping scheme (BM) and FAST
Summary
Semiconductor-chip-based nonvolatile memories (NVM) are becoming more widely used and are no longer confined to embedded systems. Overcome the above-mentioned shortcomings by combining both types of mapping It is generally based on a block-mapping scheme and uses page-mapping for a small number of blocks (see the Related Work section below). This paper describes CACH-FTL [12], a cache-aware configurable hybrid FTL designed to optimize write performance and embedded memory usage This optimization is achieved through a flexible and efficient data placement mechanism. CACH-FTL selectively places data flushed by the above cache either in the PMR or in the BMR, depending on the number of flushed pages If this number is above a (configurable) threshold, written data are considered as sequential and, directed toward the BMR; as block-mapping is well suited for large write operations with a high spatial locality (pages from the same block). The conclusions and some perspectives for future work are given
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