A Saturation Suppression Approach for the Current Transformer—Part II: Performance Evaluation

Abstract

Part I of this two-part paper introduces a hardware-based mechanism to prevent/suppress the saturation phenomenon of the current transformer (CT). The mechanism includes an electronically switched resistor which is in series with the CT secondary winding. Part II performs a set of 1) offline digital time-domain simulation studies in the PSCAD/EMTDC environment and 2) control-hardware-in-the-loop (CHIL) test cases in a real-time digital simulation platform, to demonstrate technical feasibility of the proposed approach. The investigations also report the effect of CT saturation and the proposed desaturation mechanism on a digital distance relay. The digital algorithms of the relay and the control of the electronic switch are implemented in two NI-CRIO platforms for the CHIL studies. The investigation results demonstrate and verify the effectiveness of the proposed CT desaturation mechanism.