A satisfiability formulation for FPGA routing with pin rearrangements

Abstract

This paper presents a satisfiability formulation for FPGA segmented channel routing with pin rearrangements. In our new routing model, the pins in each module have certain degree of freedom to be rearranged. With this flexibility, the wire routability can be improved in segmented channel routing. We present an efficient SAT-based approach to solve the problem. We use one of the best SAT-solvers, zChaff, to perform our experiments. Experimental results show the promising performance of the method.