Abstract
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one parametric representation to another smaller representation, in a process called reparameterization. For large circuits, the reparametrization step often results in a blowup of BDDs and is expensive due to a large number of quantifications of input variables involved. Efficient SAT solvers have been applied successfully for many verification problems. This paper presents a novel SAT-based reparameterization algorithm that is largely immune to the large number of input variables that need to be quantified. We show experimental results on large industrial circuits and compare our new algorithm to both SAT-based Bounded Model Checking and BDD based symbolic simulation. We were able to achieve on average 3x improvement in time and space over BMC and able to complete many examples that BDD based approach could not even finish.
Highlights
Symbolic simulation is a widely applied technique for the analysis of complex transition systems and synchronous circuits in particular
Bounded Model Checking (BMC) keeps on unwinding the transition relation, while we periodically reduce the size of representation with reparameterization
The method uses an unwinding of the transition relation and is comparable to BMC
Summary
Symbolic simulation is a widely applied technique for the analysis of complex transition systems and synchronous circuits in particular. An efficient way to store and manipulate this parametric representation of the set of states is crucial for the performance of the algorithm. The reparameterization is done using BDDs, as the number of simulation steps grows, the algorithm quickly becomes very expensive. We describe a SAT-based algorithm to perform the reparameterization step for symbolic simulation. The algorithm takes arbitrary Boolean equations as input It does not require BDDs for the symbolic simulation. The SAT-based reparameterization algorithm computes a new parametric function for each state variable one at a time. We demonstrate the efficiency of this new technique using large industrial circuits with thousands of latches We compare it to both SAT-based Bounded Model Checking (BMC), which unrolls the circuit for a finite number of steps and with BDD-based symbolic simulation. The symbols α and β will denote the constants 0 or 1
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have