Abstract
The main time parameters of sample-and-hold devices (SHDs)—sampling time and storage time—also cause the main disadvantages of these devices, long sampling time and short storage time, which cannot be removed by merely changing the storage condenser capacity. The circuit designs of standard SHDs, the time parameters of which are explicitly determined by the storage condenser capacity, provide only a reduction of the sampling time with a simultaneous reduction of the storage time or an increase of the storage time with a simultaneous increase of the sampling time. An attempt to increase the storage time with simultaneous invariability of the sampling time or decrease the sampling time with simultaneous invariability of the storage time led to the development of SHDs with improved time parameters. SHD time parameters are improved by forced reduction of the discharge current of the storage condenser. With invariability of sampling time, the circuit design that has been developed of arrangement of the SHD provides a more than fivefold increase of the storage time.
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