A safe single-phase clocking scheme for CMOS circuits

Abstract

A single-phase clock has two edges. A clocking scheme utilizing the two edges of a single-phase clock to control the movement of data is presented. The scheme is similar to the two-phase nonoverlapping clocking scheme. A single-phase clock CMOS shift register to illustrate this clocking schemes is proposed. This shift register utilizes the bistable element, 'sense amplifier', to sense the state of its previous stage. There are two stages. The first stage triggers on the rising edge and the second stage triggers on the trailing edge. It is a static register with no minimum clocking frequency. Instead of four clock phases used in conventional CMOS dynamic shift registers, or two clock phases used in existing static registers, only one clock phase is used. This single-phase clocking scheme greatly reduces the overhead of having to route two or four clock signals around the chip. It also eliminated the clock skewing difficulty plaguing the conventional shift register.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>