A Rule-Based Approach to Unifying Functional and Fault Simulation and Timing Verification

Abstract

A novel approach to design verification is presented that is based on a new methodology for modeling and verifying digital designs. The verification methodology unifies functional and fault simulation and timing verification into one general rule-based framework wherein functional, fault, and timing characteristics of digital designs are expressed through a set of rules. Consequently, models of new devices and for new types of simulations may be introduced into the verification system with relative ease. Introducing other types of simulations into the verifier would require expressing the appropriate characteristics of digital devices in the form of rules. This approach has been verified in the experimental RDV [GS84] system at Stanford University and the hardware-description language used is Ada [AD83]. Unification of functional and fault simulation and timing verification is made possible by a combination of distributed approaches to modeling and scheduling.