Abstract
A row-based Field Programmable Gate Array (FPGA) consists of rows of identical processing modules separated by segmented tracks that are used for routing nets between specified module pins. The problem of finding a feasible routing of a given set of nets onto a set of segmented tracks is NP-complete. We present an enumeration algorithm for the problem that uses matching arguments to improve the time complexity while requiring polynomial space. The algorithm serves as the basis of powerful practical heuristics and its additional advantage is that it is directly parallelizable.
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