A router architecture with dual input and dual output channels for Networks-on-Chip

Abstract

Networks-on-Chip (NoCs) are the most viable and scalable solution for connecting thousands of processing cores, and are emerging as the interconnect infrastructure for future Chip-Multiprocessors. Latency and throughput are the primary metrics for on-chip network performance, while chip area and power budgets are increasingly dominated by interconnect networks. Hence, it is critical to achieve higher performance gains at a lower cost. Previous research has proposed a router architecture that forwards packets through idle bidirectional channels to improve network performance, but it introduces significant area and power overheads. In this paper, we propose DIDO: a router architecture with dual input and dual output channels. First, the dual output channels provide extra flexibility for forwarding packets and reduce packet contention. Then, the redesigned input ports and crossbar shorten the pipeline and reduce the crossbar overhead. Finally, the removal of the virtual channel allocator allows DIDO to operate at higher frequencies. Simulation results indicate that DIDO reduces average packet latency by up to 44.8% and improves network throughput by up to 37.8% compared to the baseline router at the same frequency. Synthesis results indicate that the DIDO’s area and power overhead are comparable to the baseline router, while the maximum frequency is boosted by 18%.