A Robust Low-$k$/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)

Abstract

A robust Cu dual-damascene (DD) interconnect has been developed in a low-density (LD) SiOCH film (k = 2.7) with a low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> sidewall protection layer (SPL) made of plasmapolymerized divinylsiloxane-benzocyclobuten (p-BCB, k = 2.7). A thinned Ta/TaN barrier-metal (BM) structure combined with the low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> SPL was implemented. The SPL covering the DD sidewall in the LD-SiOCH film secures the spacing between the lines and vias, and makes low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> surface smooth which enhances the BM coverage on the DD sidewalls. As a result, the leakage yield against via misalignment and the insulating reliability such as time-dependent dielectric breakdown between the DDIs, particularly with vias, are improved. With our special p-BCB SPL, the BM was able to be thinned to half as thick as the conventional one, reducing resistances of the vias and the line and the interconnect RC delay without any degradation in the via electromigration reliability. The combination of the low-k SPL with the thin BM is a key for scaled-down robust LSIs with Cu DDIs in low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics.