A Robust Location Algorithm for PCB's Solder Joints

Abstract

Printed circuit boards (PCBs) are being widely used in the electronic packages. Solder joints are often used to interconnect chip resistors and other components onto PCBs. The defects of solder joints will increase quality costs and deteriorate performance. If solder joints cant be located accuracy, AOI system will not inspect solder joints at the right place of solder joints and must lead to misjudgement. Especially, the misjudgement will increase dramatically under uncertain noise disturbance to micro-size solder joints due to inaccuracy location. In this work, an eliminating uncertain noise method is proposed and a robust location algorithm for PCBs solder joints is present. Firstly, some location windows are set based on technology parameters of chip and its solder joints, and solder joints feature image is obtained from it solder joint image based on series of image pre-processing. Secondly, the layout frame outside solder joints, which is viewed as a noise disturbance to location, is extracted as a binary image and is projected to X axis and Y axis, then the smaller region, which include solder joints but no the layout frame, is obtained based on calculating the sum features function of layout frame. Thirdly, the blob feature image of solder joints is extracted from its gray images of red, green, blue layers; it may have some noise blob around solder joints feature, then an evaluation function is develop to judge blob, which maybe belongs to noise or solder joints feature, and only solder joints feature are remained. Fourthly, with the help of setting solder joints windows, the integrated projection method is developed to locate solder joints. Finally, the proposed location method is compared with other two algorithms in the experiment. Experiments result illustrates that the smaller the solder joint size, the better location accuracy and efficiency is obtained than other two mothers.