A robust handshake for asynchronous system

Abstract

In this paper, a new handshake methodology to enhance the performance of the asynchronous systems is proposed. The proposed handshake methodology has more flexibility to design an asymmetric asynchronous system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. In others the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. Finally, an asynchronous array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 /spl mu/m CMOS technology, the simulation result of the maximum throughput is about 2.5 ns.