Abstract
We describe a process used successfully to fabricate large second-order planar gradiometers with integrated DC SQUIDs on two-inch silicon wafers. All the refractory materials (Nb, Mo and SiO/sub 2/) are deposited by magnetron sputtering. The Josephson junctions are based on the well-established Nb/AlO/sub x//Nb trilayer technology. All Nb layers are patterned by Reactive Ion Etching using a procedure optimized by experimental design. Since only one gradiometer can fit on a wafer, extra care had to be taken in both the design of the device and the fabrication process to ensure that the yield was high. Excellent process latitude is achieved by sufficient built-in design margins to accommodate any tolerance difficulties during fabrication. >
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