Abstract

In recent years, public-key cryptography has become a fundamental component of digital infrastructures. Such a scenario has to face a new and increasing threat, represented by quantum computers. It is well known that quantum computers in the next years will be able to run algorithms capable of breaking the security of currently widespread cryptographic schemes used for public-key cryptography. Post-quantum cryptography aims to define and execute algorithms on classical computer architectures, able to withstand attacks from quantum computers. The National Institute of Standards and Technology is currently running a selection process to define one or more quantum-resistant public-key algorithms and lattice-based cryptographic constructions are considered one of the leading candidates. However, such algorithms require non-negligible computational resources to be executed. One viable solution is to accelerate them totally or partially in hardware, to alleviate the workload of the main processing unit. In this paper, we investigate a solution trading-off performance and complexity to execute the lattice-based algorithms CRYSTALS-Kyber and -Dilithium: we introduce a dedicated Post-Quantum Arithmetic Logic Unit, embedded directly in the pipeline of a RISC-V processor. This results in an almost negligible area overhead with a large impact on the algorithms speed-up and a consistent reduction in the energy required per single operation.

Highlights

  • In the last years, a digitalization process is going on in many different areas like industry 4.0, automotive, and healthcare

  • In State of the Art (SoA) systems, the security of the connections relies on the Public Key Cryptography (PKC) which employs a pair of keys, public and private

  • We propose a first Instruction Set Architecture (ISA) extension to the CVA6 [10] processor, applicable to other processors of the RISC-V family, to accelerate the execution of the CRYSTALS-Kyber and -Dilithium algorithms, respectively a Key Encapsulation Mechanism (KEM) and a Digital Signature Scheme (DSS)

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Summary

INTRODUCTION

A digitalization process is going on in many different areas like industry 4.0, automotive, and healthcare. Post-Quantum Cryptography (PQC) exploits mathematical elements and operations which are usually not straightforward to implement on standard processors This is a critical aspect especially in low-power embedded devices that have a limited amount of resources and computational power. A classical approach is to design and embed hardware accelerators connected to the control and elaboration unit as memory-mapped peripherals [6] Another option is to bring smaller hardware accelerators directly in the processor pipeline [7]. We propose a first ISA extension to the CVA6 [10] processor, applicable to other processors of the RISC-V family, to accelerate the execution of the CRYSTALS-Kyber and -Dilithium algorithms, respectively a Key Encapsulation Mechanism (KEM) and a Digital Signature Scheme (DSS).

KYBER AND DILITHIUM OVERVIEW
CRYSTALS-DILITHIUM
NTT AND MODULAR REDUCTIONS
PERFORMANCE TESTS
RESULTS
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