A RISC architecture for high-speed data acquisition

Abstract

A RISC architecture specifically designed for selective storage of high-speed digital words is presented. A specialized instruction set is created to allow programmable control of trigger conditions and storage memory. A RISC architecture is required to execute the instruction set and maintain a 10-MHz sample rate. The utility of the RISC system is illustrated by implementing both analog and digital data acquisitions. A prototype system was designed and fabricated for evaluation. Features of this design are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>