Abstract
The output ripple of switched-capacitor dc–dc voltage converter (SCVC) severely degrades the energy efficiency, performance, and robustness of the VLSI system. In this paper, a fully digital resistance modulation (FDRM) technique is proposed to reduce the output ripple of SCVC, which is scalable and compatible with the exiting ripple reduction methods. The proposed FDRM technique suppresses the impulsive charging and discharging effects in the SCVC operation by dynamically modulating its equivalent switch resistances, resulting in a reduced output ripple. The FDRM control signals can be generated from simple logic gates with the interleaved clock signals, realizing a low implementation complexity. The proposed FDRM technique was verified by a fully integrated SCVC in 180-nm CMOS process with an active area of 0.93 mm2. The measurement results show that the SCVC prototype with the proposed FDRM technique achieves an averaged ripple reduction of 31.6% and a peak conversion efficiency of 88.96% under a loading range of 95–190 $\mu \text{A}$ .
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